What AWS actually shipped
On June 30, 2026, Amazon Web Services announced Graviton5, the fifth generation of its in-house Arm server silicon, and made it available in the first EC2 instances built on it: the compute-optimized C9g and C9gd families. The headline claim is up to 25 percent higher performance per vCPU against the previous-generation C8g, backed by a 5x larger L3 cache and up to 3x higher packet-processing throughput versus Graviton4-based instances.
These are not incremental spec-sheet tweaks. Cache size and memory throughput are precisely the constraints that bite compute-optimized workloads such as ad-serving, real-time bidding, application servers and batch analytics. AWS pairs the new core with DDR5 memory clocked at 8800 MT/s, which it describes as the fastest of any cloud processor instance, and adds roughly 20 percent more EBS bandwidth on average and up to 15 percent more network bandwidth across sizes.
The shape of the lineup
C9g and C9gd ship in 11 sizes from medium up to 48xlarge, plus a bare-metal option. The top 48xlarge configuration offers 192 vCPUs, 384 GiB of memory and up to 100 Gbps of networking, with up to 72 Gbps of EBS bandwidth. The C9gd variant adds local NVMe storage and up to 30 percent higher storage performance for workloads that need fast scratch space next to the compute.
The breadth matters as much as the peak. A family that spans a single vCPU to 192, with a bare-metal rung for licensing-sensitive or hypervisor workloads, is designed to absorb an entire fleet rather than a niche. For an operator, that means fewer exceptions to reason about when standardizing on a single instance generation.
Why the price-performance gap keeps widening
Graviton exists because AWS controls the design and pays no third-party CPU margin. Each generation has narrowed the reasons to stay on x86, and Graviton5 pushes the frontier further into the territory where the Arm option is simply the default rational choice for new compute-optimized capacity. The 25 percent per-vCPU gain compounds directly against a bill: the same throughput on fewer or smaller instances.
The competitive pressure runs both ways. Intel and AMD still hold the installed base and the widest software certification, and plenty of enterprise workloads remain pinned to x86 by vendor support matrices. But the direction of travel is unambiguous. When the in-house part leads on cache, memory speed and packet processing at the same time, the burden of proof shifts to those who want to keep buying the merchant silicon.
What this means for EU operators
Frankfurt is a launch region alongside US East (Ohio, N. Virginia) and US West (Oregon), which is the detail EU owners should read closely. Availability in an in-region location removes the latency and data-residency friction that often delays European adoption of new US-first hardware. Compute-optimized workloads running in eu-central-1 can be tested against Graviton5 now, not in some later wave.
The practical move is unglamorous but material: benchmark your hottest compute-bound services on C9g, measure the real per-vCPU delta on your own code rather than the marketing figure, and model the migration cost against the recurring saving. Arm-native builds are now routine across the major language runtimes, so the porting tax that once justified inertia has largely evaporated.
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