SK Hynix Names Interconnect as AI's Next Bottleneck

The Bandwidth Wall Behind the Compute Race

AI infrastructure buyers have spent two years comparing GPU counts and FLOPS while a quieter constraint closed in around them: SK hynix's own published roadmap now states that compute throughput has roughly tripled every two years, while interconnect bandwidth, the data links between memory and processors, has advanced only about 1.4x over the same period. That imbalance has been invisible in most procurement conversations, which for two years have revolved almost entirely around GPU counts, FLOPS, and, more recently, HBM capacity, with the wiring between chips barely mentioned in a request for proposal.

That gap is what the company's engineers call a bandwidth wall. Conventional copper interconnects run into inherent physical limitations as the distance between chips grows, so a cluster with more GPUs than ever can still starve for data the moment those chips need to talk to each other across a rack or a board. The paper's framing is blunt: interconnect, not raw compute, is becoming the binding constraint on AI infrastructure performance. The physics behind that limitation is straightforward: as a copper trace or cable gets longer, the signal it carries loses strength to resistance and picks up electrical noise from neighboring lines, so engineers either slow the signal down or spend disproportionate power pushing it through, and at rack and data-hall distances that tradeoff is no longer favorable.

What SK Hynix's Roadmap Actually Promises

The roadmap appears in a peer-reviewed paper, Co-packaged optics for high-performance computing and artificial intelligence, published in Nature Electronics and co-authored with the University of Virginia, the University of Illinois Urbana-Champaign, Nanyang Technological University, MIT, and Yonsei University. It sets three concrete targets for next-generation AI infrastructure built around co-packaged optics, or CPO: more than 100 Tb/s of bandwidth per node, energy consumption below 1 picojoule per bit, and chip-to-chip latency under 10 nanoseconds. The five-university author list, spanning the United States, Singapore, and South Korea, signals that this is being treated as a shared engineering challenge across the industry rather than a single company's internal target.

CPO reaches those numbers by physically integrating optical engines into the same package as the processor or memory, replacing separate pluggable optical transceivers and the electrical copper links that feed them. Shortening the electrical distance a signal has to travel cuts both the energy lost to resistance and the time lost to transmission, which is why the roadmap's three targets move together rather than trading off against each other. That matters because most attempts to fix one part of the bandwidth wall, wider copper traces, more parallel lanes, higher clock speeds, tend to worsen energy use or latency elsewhere; CPO is presented as a way to move all three figures in the right direction at once.

Why This Is a Procurement Problem, Not Just an Engineering One

For the past two years, AI infrastructure purchasing decisions, cloud contracts, on-prem GPU clusters, colocation deals, have been evaluated almost entirely on compute and, more recently, on memory capacity and bandwidth. SK hynix's own roadmap is effectively a public admission that the next bottleneck, and therefore the next point of vendor lock-in and pricing leverage, sits in the interconnect layer that most enterprise buyers do not currently evaluate at all. A typical cloud or GPU-cluster request for proposal today asks about accelerator generation, memory bandwidth, and power draw per rack, but rarely asks a vendor to describe its interconnect or CPO roadmap at all.

The consequence for a European business signing a multi-year AI infrastructure or cloud contract is concrete: a cluster that looks future-proof on GPU count and HBM capacity today can become bandwidth-starved well before it becomes compute-starved. Whichever supplier controls the optical interconnect layer, not just the chip, stands to hold outsized pricing power over the next hardware refresh cycle. Most enterprise AI infrastructure contracts already run three to five years, which means a decision made this year is a decision about which supplier holds that leverage through roughly 2029 or 2030.

What to Ask Before Your Next Renewal

Procurement and infrastructure teams evaluating cloud or AI hardware vendors should start asking about interconnect and CPO roadmaps now, not when the current contract comes up for renewal. That means asking a vendor directly how it plans to move data between memory and compute at scale, not only how many accelerators it can rack, and asking for a timeline rather than a slide of intentions. Three concrete questions belong on that checklist: what is the vendor's current interconnect bandwidth per node, what is its published CPO or optical-interconnect roadmap, and how does that roadmap compare with the 100 Tb/s, sub-1-picojoule, sub-10-nanosecond targets SK hynix has now put into the public record.

SK hynix publishing this work under its own newsroom, alongside five universities and a peer-reviewed journal, reads as a memory supplier repositioning itself as a systems-level AI infrastructure company. Buyers who treat that shift as background noise will negotiate their next refresh from a position of knowledge gaps; buyers who put interconnect on the evaluation sheet today negotiate from a position of strength. Treating this roadmap as a memory-industry curiosity rather than a procurement signal is the mistake most buyers are still making, and it is the mistake this roadmap was published to correct.

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