Infrastructure

Cadence And Synopsys Tuned Their Tools For Nvidia

Nvidia says its own Vera CPU runs Cadence and Synopsys verification up to 1.5x faster. The number is Nvidia's, and the design farm question is now open.

InfrastructureBy Servola Tech Desk2026-07-275 min read

AI-assisted, edited by humans. | Editor-in-Chief: Leon Soliman | Editorial standards

Cadence And Synopsys Tuned Their Tools For Nvidia

Key takeaways

On 26 July Nvidia said it is running its own Vera CPU across the electronic design automation workflows it uses to build its next generation of CPUs and GPUs, with Cadence Jasper and Synopsys VCS showing up to 1.5 times higher performance on selected production workloads. The two firms whose tools most chip designers rent have now optimised them for one vendor's processor.
Verification and regression are the longest pole in any tape-out schedule, which is exactly where the claimed gain sits: logic simulation, formal verification, digital implementation and regression testing. A durable 1.5x there is weeks of calendar time, not a benchmark curiosity.
Every figure in the announcement is vendor-reported and none has been independently verified. Nvidia did not state whether Vera is available to external customers, and the partner numbers around it, including Keysight at up to 10 times on electromagnetic simulation with cuDSS, come through the same channel.
Before your next design farm refresh, require a benchmark on your own regression suite rather than the vendor's, and ask Cadence and Synopsys in writing what support and feature parity they commit to per architecture. A tool that is fastest on one CPU is a procurement decision, not a technical detail.

The loop Nvidia just closed

Nvidia published the claim on 26 July: it has deployed its Vera CPU across the electronic design automation workflows used to develop its next generation of CPUs and GPUs. The chip is designing its successor. Vera carries 88 custom Olympus cores, an LPDDR5X memory subsystem and a second generation Scalable Coherent Fabric, and it is the first CPU core Nvidia designed in house rather than licensing a standard design.

The part that reaches beyond Nvidia is who else is in the announcement. Cadence and Synopsys, the two companies that between them supply the tools almost every semiconductor design team in the world depends on, have been working with Nvidia on application profiling, software optimisation and system-level tuning. Cadence's Jasper formal verification platform and Synopsys VCS functional verification both showed up to 1.5 times higher performance on Vera on selected workloads. A companion announcement the same day extended Nvidia's Agent Toolkit with the PhysicsNeMo and CUDA-X libraries, with partner figures attached: Keysight reporting up to 10 times faster electromagnetic simulation using new cuDSS libraries, Silvaco completing a complex photonic simulation in under four hours on a cluster of 32 GPUs, and Cadence citing a 15 times increase on design verification workflows using cuDSS on its own supercomputer.

This is a compounding advantage, not a product launch. A company that makes its own silicon, then uses that silicon to shorten the design cycle of the next generation, has bought itself time that its competitors cannot rent. AMD and Intel run the same Cadence and Synopsys tools, but neither sells itself a CPU that those tools have been jointly tuned for. The interesting disclosure here is not a benchmark. It is that the industry's design toolchain now has a preferred architecture, and its owner is a participant in the market it serves.

What 1.5x is measured on, and by whom

Take the number seriously and then take it apart. The workloads named are logic simulation, formal verification, digital implementation and regression testing, and that list is not incidental. Verification consumes the majority of the engineering effort in a modern complex design, and regression runs are the thing that determines whether a schedule holds. A team that shortens verification does not merely save compute. It gets more attempts at finding the bug that would otherwise be found after tape-out, which is where the cost of a mistake multiplies.

The number is Nvidia's own. The 1.5 times figure comes from Nvidia's testing on selected production-class workflows and has not been independently verified. The same applies to the partner figures in the companion release, which arrive through Nvidia's channel rather than from a neutral evaluator. None of that makes them false, and the involvement of Cadence and Synopsys in the optimisation work means real engineering was done. It does mean the claims describe a best case chosen by the party with the strongest interest in the result.

There is a second gap worth naming. The announcement describes internal deployment at Nvidia and does not state whether Vera is available to external customers or on what terms. So an outside team reading a 1.5x result cannot currently act on it in the way the framing invites. The Vera Rubin platform is in production, but production for a platform sold as an integrated system is not the same as a CPU you can put in a design farm rack next quarter.

What this changes for a European design house

Europe still designs a great deal of silicon even though it fabricates less than it would like. Infineon, NXP, STMicroelectronics, Bosch and Arm all run large design organisations, the EU Chips Act has funded design capacity alongside fabrication, and a long tail of fabless teams rents time on shared compute. Every one of those organisations licenses Cadence or Synopsys tools, and for every one of them the verification farm is a capital line that gets revisited on a multi-year cycle. That refresh has been an x86 decision by default for two decades. It is now a question with two answers, and the evidence for the newer answer comes from the company selling it.

Where the time actually goes. Before treating a 1.5x claim as a plan, establish what your own bottleneck is. In many design organisations the constraint is not raw per-core throughput but licence seats, queue scheduling and the serialisation of regression against a shared farm. A faster CPU under a licence model that caps concurrent runs delivers a fraction of the headline. Work out which of those binds first, because if it is the licence rather than the silicon, the architecture question is premature and the negotiation you need is with the tool vendor.

Ask for the benchmark on your own suite. Two requirements make this decidable. Require a proof of concept measured on your regression suite and your design database, not on a vendor's selected workflow, with the licence configuration you actually run. And get Cadence and Synopsys to state in writing what support and feature parity they commit to per architecture over the life of your agreement, because a tool that is fastest on one CPU today becomes a lock-in question the moment your farm is built around it. The engineering claim may well hold. The procurement exposure is the part that does not appear in any benchmark.

Frequently asked questions

Does this mean x86 is finished in chip design?

No, and nothing in the announcement supports that reading. It establishes that a credible alternative now exists in a domain that was effectively single-architecture, backed by optimisation work from the two dominant tool vendors. That is a meaningful shift in optionality rather than a displacement. Established farms will run x86 for years, and the decision point arrives at refresh, not immediately.

Why does it matter that Nvidia designs its own chips faster?

Because design cycle time is one of the few advantages in semiconductors that competitors cannot buy. Manufacturing capacity can be contracted and intellectual property can be licensed, but the number of iterations a team completes before a deadline is set by its own tooling. If Nvidia compounds a shortened cycle across several generations, the gap it opens is structural rather than a matter of any single product being better.

Should we raise this with our EDA vendor now?

Yes, and the reason is timing rather than urgency. The useful conversation happens while you still have a renewal in front of you, since that is when a commitment on cross-architecture support and licensing terms is negotiable. Ask what is supported today, what is committed for the term, and what happens to your licence entitlement if you move part of the farm. Those answers age badly once the purchase is made.

The headline result is a benchmark, and benchmarks from an interested party deserve the usual discount. The durable fact underneath it is structural: the tools that verify most of the world's silicon have been tuned for a processor made by a company that competes with many of the teams using them. That is a new dependency in a supply chain already short of alternatives, and it will be priced into design farm decisions for the rest of the decade. Establish your own numbers on your own workloads before the architecture choice is made for you by a refresh cycle.

NvidiaCadenceSynopsysVera CPUEDAchip designsemiconductorsvendor lock-in

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