Infrastructure

512 Gigabytes Now Sits Between HBM and the SSD

The first High Bandwidth Flash specification landed through the Open Compute Project: up to 512GB, three grades from 0.4 to 3.0 TB/s, on a UCIe interface. It is the industry routing around the HBM shortage.

InfrastructureBy Servola Tech Desk2026-08-045 min read

AI-assisted, edited by humans. | Editor-in-Chief: Leon Soliman | Editorial standards

512 Gigabytes Now Sits Between HBM and the SSD

Key takeaways

SK hynix and Sandisk published the first High Bandwidth Flash specification through the Open Compute Project on 3 and 4 August, defining up to 512GB per stack at 0.4 to 3.0 terabytes per second, which creates a memory tier between HBM and the SSD built on NAND rather than DRAM.
Ask your accelerator and server vendors now whether their 2027 platforms include an HBF tier, because HBF connects over UCIe as a chiplet interface and is therefore designed in at the silicon level rather than added to a system later.
The three defined grades span 0.4 to 3.0 terabytes per second, a 7.5 fold spread, which means the standard is a cost and performance ladder rather than a single part you either buy or do not.
The specification was published roughly six months after the consortium began work in February 2026, and it arrived before volume silicon, so the standard is settled while procurement decisions for 2027 are still open.
SK hynix also disclosed its tenth generation 375 layer NAND with a claimed 2.5 times improvement in power efficiency and mass production of high performance enterprise drives planned for early 2027.

What the OCP specification actually defines

Sandisk and SK hynix released the first technical specification for High Bandwidth Flash through the Open Compute Project, Sandisk announcing on 3 August and SK hynix presenting at the Future of Memory and Storage conference in Santa Clara, which runs from 4 to 6 August. The specification covers capacities up to 512GB using either 8 high or 16 high NAND die stacks, three performance grades delivering roughly 0.4 to 3.0 terabytes per second of read bandwidth, and a UCIe interface for integration with processors.

The document is more than a datasheet. It defines the host interface between the processor and the HBF stack, the electrical characteristics, reliability guidance, packaging requirements for the die stack process, and a software guide for read and write operations. In other words it specifies the parts a system designer needs in order to build a board around a component that does not yet ship in volume. SK hynix executive vice president Kim Chun-sung framed the purpose as expanding the boundaries between memory and storage, and the company used the same event to disclose a tenth generation 375 layer NAND with a claimed 2.5 times power efficiency gain, with enterprise drives based on it due in early 2027.

A 7.5 fold spread across three grades is the tell

The specification's most revealing number is the range. Grade one delivers about 0.4 terabytes per second and grade three about 3.0, which is a 7.5 fold spread inside a single standard. Memory standards do not usually stretch that far. A spread that wide says the authors are not defining one component, they are defining a ladder, with a cheap high capacity rung for holding model weights and a fast rung that competes for work currently done by high bandwidth memory.

That is the strategic content of this announcement, and it is worth stating plainly: HBF exists because the industry cannot get enough HBM. Our own reading of the memory market over recent weeks has been consistent on this point, with the great majority of advanced memory supply already committed well ahead of delivery. HBM is fast, small and allocated. NAND is slower per bit but enormously more abundant and not fully spoken for. Putting a NAND stack behind a high bandwidth interface is an attempt to buy capacity in the one currency still available. The 512GB figure matters more than the 3.0 terabytes per second, because capacity is what inference workloads run out of first when context windows and model weights grow.

Google and Tenstorrent are the signatures that matter

Two memory manufacturers agreeing on a standard proves very little on its own, since both sell the thing being standardised. The consequential detail is that Google and Tenstorrent joined the consortium during the standardisation process and contributed to validating the technology. One is a hyperscaler that buys accelerators in volume and designs its own, the other designs accelerators. Their presence turns the specification from a supply side proposal into something with demand side commitment attached.

The timing reinforces that. The consortium started work in February 2026 and published roughly six months later, which is quick for a memory interface, and it published before volume parts exist. Standardising first and shipping second is the opposite of the usual sequence, where a dominant vendor ships a proprietary part and the standard follows to bless it. Publishing through the Open Compute Project also means the interface is open to competing NAND suppliers, which is the mechanism most likely to prevent HBF from repeating the allocation squeeze that HBM created. For European buyers pursuing supply resilience under the Chips Act, an open interface with multiple potential sources is a materially better starting position than a single vendor roadmap.

The procurement question for 2027

Because HBF attaches over UCIe, a chiplet interconnect, the decision to include it is made when the accelerator or the module is designed. It is not a card you add to a server you already own, and it is not a retrofit. That places a specific question on your desk in the next procurement cycle rather than in 2028: does the platform we are about to commit to for the next four years have an HBF tier, and if it does not, what happens to our inference cost per token when memory capacity becomes the binding constraint.

The honest caveat is that a published specification is not silicon. No volume HBF part has shipped, the performance grades are design targets, and standards have died between publication and production before. Treat this as a reason to ask vendors a pointed question and to insist on a roadmap answer in writing, not as a reason to delay a purchase you need now. The right posture is to avoid signing a long platform commitment that assumes the memory hierarchy of 2026 will still be the memory hierarchy of 2028, because the people who make the memory have just published a document saying it will not be.

Frequently asked questions

Is HBF a replacement for HBM?

No, and the specification is explicit that it is designed to coexist with high bandwidth memory rather than displace it. HBF is built on NAND, which is slower per bit and has different endurance characteristics than DRAM, so the intended role is a large capacity tier beneath HBM for data that must be reached quickly but not at HBM latency. Think of it as a new rung on the ladder rather than a swap.

What does publishing through the Open Compute Project change?

It makes the interface public and implementable by parties who did not write it, which opens the door to competing NAND suppliers building compatible stacks. That matters for buyers because it is the main structural difference between a component that becomes broadly available and one that becomes allocated to the largest customers. It also means system designers can begin engineering against the document now rather than under a supplier agreement.

Should we delay a 2026 hardware purchase because of this?

Generally no. Nothing has shipped in volume, the grades are design targets, and capacity you need this year is worth more than an option on a component that may arrive in 2027. The defensible action is to avoid long platform lock in that assumes today's memory hierarchy, and to get a written answer from your accelerator and server vendors about whether their 2027 designs include an HBF tier.

A standard published before the silicon exists is a statement about scarcity, not about performance. Two memory makers, a hyperscaler and an accelerator designer spent six months agreeing how to hang 512 gigabytes of NAND off a high bandwidth interface, because the memory everyone actually wants is sold out years ahead. The number to carry into your next hardware negotiation is not 3.0 terabytes per second. It is the question of whether the platform you are about to buy has anywhere to put a tier that did not exist when it was designed.

SK hynixSandiskHigh Bandwidth FlashOpen Compute ProjectNANDHBMInferenceEU Chips Act

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